An embodiment of the present disclosure relates to a solid-state imaging device, an electronic device equipped therewith, and a manufacturing method for the solid-state imaging device.
Previously, as a solid-state imaging device, there have existed active pixel sensors (APSs) each of which is equipped with an amplifying element with respect to each pixel. In recent years, among them, complementary MOS (CMOS) image sensors where signal charge accumulated in a photodiode serving as a photoelectric conversion element is read through a metal-oxide-semiconductor (MOS) transistor have been used for various purposes.
The CMOS image sensor includes a substrate in which a photodiode subjecting incident light to photoelectric conversion is formed and a wiring layer formed on the substrate. In addition, at present, front-side illumination type CMOS image sensors are widely used where a photodiode is irradiated with light from a substrate surface on the wiring layer side of the substrate.
In addition, recently, so as to improve the sensitivity of a photodiode, back-side illumination type CMOS image sensors have also been proposed where a photodiode is irradiated with light from a substrate surface (back surface) on a side opposite to the wiring layer side of a substrate. An example of such a technique has been disclosed in Japanese Unexamined Patent Application Publication No. 2003-31785 or Japanese Unexamined Patent Application Publication No. 2008-103668.
FIG. 19 illustrates a schematic cross-sectional view in the vicinity of a photodiode in the back-side illumination type CMOS image sensor proposed in Japanese Unexamined Patent Application Publication No. 2003-31785. A photodiode 601 is formed within a silicon layer 600. In addition, the photodiode 601 includes an N− region 601a, an N+ region 601b accumulating therein signal charge (electrons), formed on the N− region 601a, and a P+ layer 601c formed on the N+ region 601b. In addition, a shallow P+ layer 602 is formed on a surface on the light incidence side of the photodiode 601, and a deep P well 603 to be a pixel separation layer is formed in the side portion of the photodiode 601.
Namely, the back-side illumination type CMOS image sensor in Japanese Unexamined Patent Application Publication No. 2003-31785 has a structure in which the N type impurity region of the photodiode 601 is surrounded by a P type impurity layer. In particular, on the substrate surface side of the N type impurity region of the photodiode 601, the high impurity concentrated P+ layer 601c is formed, and the photodiode 601 in Japanese Unexamined Patent Application Publication No. 2003-31785 has a hole accumulated diode (HAD) type structure suppressing the occurrence of a dark current due to surface generation recombination.
In addition, in the back-side illumination type CMOS image sensor in Japanese Unexamined Patent Application Publication No. 2003-31785, the signal charge, subjected to photoelectric conversion in the photodiode 601 and accumulated in the N+ region 601b, is transferred by a transfer transistor 604 to a floating diffusion region 605 in an N+ type region.
In addition, here, for comparison, FIG. 20 illustrates a schematic cross-sectional view in the vicinity of a photodiode in a front-side illumination type CMOS image sensor described in Japanese Unexamined Patent Application Publication No. 2003-31785. A pixel portion 700 in the front-side illumination type CMOS image sensor includes an N type silicon substrate 701, a wiring layer 702 formed on the light incidence side of the N type silicon substrate 701, and a passivation film 703 formed on the light incidence side of the wiring layer 702. In addition, in the vicinity of a surface on the light incidence side of the N type silicon substrate 701, a P well region 704 is formed, and a photodiode 705 is formed so as to be embedded in the surface of the P well region 704. In addition, while not illustrated in FIG. 20, the N type silicon substrate 701 is connected to an applying terminal for a power source voltage Vdd, for example.
In the front-side illumination type CMOS image sensor illustrated in FIG. 20, in the bottom portion of an N type layer, in which the photodiode 705 is formed, the P well region 704 is formed that is to be a potential barrier for electrons generated in the photodiode 705. In addition, the potential barrier of the P well region 704 is set so as to be lower than the potential barrier of an element isolation portion (not illustrated) or a transfer gate (TG). In this case, in a direction from the photodiode 705 to the N type silicon substrate 701, an overflow path is formed that prevents electrons overflowing from the photodiode 705 (hereinafter, referred to as surplus electrons) from entering an adjacent pixel when high-intensity light is radiated. Namely, in the front-side illumination type CMOS image sensor illustrated in FIG. 20, the surplus electrons of the photodiode 705, which has occurred at the time of receiving light, is discharged across the potential barrier of the P well region 704 to the N type silicon substrate 701 connected to the applying terminal for the power source voltage Vdd or the like.
On the other hand, in the back-side illumination type CMOS image sensor illustrated in FIG. 19, since the back surface side of a substrate is subjected to light, the back surface side of the substrate is polished (thin-walled) owing to chemical mechanical polishing (CMP) processing until the thickness of the substrate reaches about 10 μm. Therefore, in the back-side illumination type CMOS image sensor, it is difficult to provide an N type substrate region in a region on the light incidence side of the photodiode 601 in the same way as the front-side illumination type CMOS image sensor illustrated in FIG. 20.
Namely, in the back-side illumination type CMOS image sensor, it is difficult to discharge the surplus electrons of the photodiode 601 to an N type substrate in the same way as in the front-side illumination type CMOS image sensor. As a result, in the back-side illumination type CMOS image sensor, when electrons, which have been generated owing to photoelectric conversion at the time of receiving light, exceed a predetermined amount of electrons capable of being accumulated in the photodiode 601, surplus electrons flow into the photodiode of an adjacent pixel. In this case, for example, a problem occurs where blooming, color mixture, or the like occurs.
Previously, so as to solve the above-mentioned problem, there has been proposed a technique where, in a back-side illumination type solid-state imaging device, a contact is formed in the upper portion of a photodiode and the surplus electrons of the photodiode are discharged to the outside of a pixel through the contact. An example of such a technique has been disclosed in Japanese Unexamined Patent Application Publication No. 2008-103668.